IEEE Electron Device Letters publishes an open-access paper "
A 0.27e− rms Read Noise 220-μV/e− Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process" by Min-Woong Seo, Shoji Kawahito, Keiichiro Kagawa, and Keita Yasutomi. "
To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node:"
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Proposed HCG pixel. (a) Cross-section of the proposed pixel for
reducing the parasitic capacitance of floating diffusion. (b) Potential
diagram as a function of the voltage level of VRTH. |
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Photoelectron-counting histrograms with a theoretical Poisson
distribution of the developed CMOS imager (@ 100,000 points,
230 LSB/e− using internal ADC). (a) Signal level λ = 2.05.
(b) Signal level λ = 4.0. |
This is close to 0.22e- rms noise reported in an
earlier paper.
Thanks to EF for the link!
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